The field of semiconductor memory devices is enormously active and rapidly developing. Various categories and sub-categories of semiconductor devices are known and commercially available. The ever-increasing popularity and ubiquity of computers and computer-based devices, both in the consumer and industrial realms, is such that the demand for semiconductor memory devices of a variety of different types will continue to grow for the foreseeable future.
One of the more common categories of semiconductor memory devices used today is the dynamic random access memory, or DRAM. Among the desirable characteristics of any DRAM are a high storage capacity per unit area of semiconductor die area, fast access speeds, low power consumption, and low cost.
One approach that has been used to optimize the desirable properties of DRAMs has been to design such devices such that they are accessible synchronously. A synchronous DRAM typically requires an externally-applied clocking signal, as well as other externally-applied control signals whose timing must bear certain predetermined relationships with the clock signal. Likewise, digital data is read from and written to a synchronous memory device in a synchronous relationship to the externally-applied clock signal. Synchronous DRAM technologies have been under development for many years, and synchronous DRAMs (frequently referred to as “SDRAMs”) are used in a broad spectrum of commercial and industrial applications, including the personal computer industry.
In typical implementations, the external clock signal CLK comprises a simple, periodic “square” wave oscillating with reasonably uniform periodicity between a logical high voltage level (for example, 3.3V) and a logical low level (typically 0V) with a duty cycle of 50% (meaning that the signal is at a logical “high” level the same amount of time that it is at a logical “low” level during each complete clock cycle). In present state-of-the-art semiconductor devices, the clock signal may have a frequency on the order of hundreds of megahertz.
A synchronous semiconductor device such as a SDRAM will typically require an external input signal such as a clock signal to be provided to several (or even numerous) separate but interrelated functional subcircuits of the device. As a matter of ordinary semiconductor device layout, it is typical for each of the separate subcircuits of an overall device to be physically disposed at different and perhaps distributed locations throughout the substrate as a whole. This means that the conductive lengths, and hence such characteristics as capacitive and complex impedance loads of the various conductive traces which carry electrical signals throughout the substrate, will vary from signal to signal. Hence, for example, the propagation delay of a clock signal from a clock signal input pin to one functional subcircuit may be different than the propagation delay to another functional subcircuit; such differences can be critical for devices operating at very high clock rates, on the order of 100 MHz or so (and perhaps less).
To address such considerations, an approach referred to as “delay-locked loop” or “DLL” can be employed. In a simple example of DLL implementation, an externally-applied clock signal CLK is applied to an input pin of a memory device, and ultimately is applied to a DLL block. The DLL block operates to derive a plurality of separate internal clock signals which are then provided to the various subcircuits of memory device on various lines. The function of DLL block (which may be distributed throughout the area of the substrate) is to adjust the relative timing of the clock signals provided on the lines to the various distributed subcircuits of the device such that overall synchronous operation of the device can be achieved.
DLL blocks may utilize some type of loop-back operation, whereby the DLL block is provided with feedback for comparing the timing of the clock signal supplied to a command block with the timing of the external clock signal CLK. Since a command input buffer and a data input buffer on the memory device each receive and operate based on a clock signal, the command input pins and data input pins are said to be synchronous inputs. As such, binary data applied to such input pins will only be stored in respective buffers (a process sometimes referred to as “signal capture”) upon a rising or falling edge of the corresponding internal clock signal.
As a result of the functionality of a typical DLL circuit, if the propagation and loading characteristics of the lines varies significantly, the DLL circuit can account for such differences to ensure that proper device operation can be maintained. Internally to the DLL circuit, separate delays and skews (programmable, or automatically adjusted) may be introduced into the externally-applied clock signal to ensure that each of the other functional blocks in the device receives clock signals that are substantially synchronized with the others. The delays and skews introduced by a DLL may be miniscule, on the order of picoseconds, but may be nonetheless critical to the proper operation of a semiconductor device.
The functionality of DLLs can be thought of generally as a process of internal clock signal generation, and those of ordinary skill in the art will doubtless be familiar at least generally with the concept of DLLs in semiconductor devices. Various examples of DLL implementations for synchronous memory devices are proposed in U.S. Pat. No. 5,920,518 to Harrison et al., entitled “Synchronous Clock Generator Including Delay-Locked Loop;” U.S. Pat. No. 6,201,424 to Harrison, entitled “Synchronous Clock Generator including a Delay-Locked Loop Signal-Loss Detector;” and U.S. Pat. No. 6,130,856 to McLaury, entitled “Method and Apparatus for Multiple Latency Synchronous Dynamic Random Access Memory.” The aforementioned '518, '424, and '856 patents are each commonly assigned to the Assignee of the present invention and each are hereby incorporated by reference herein in their respective entireties.
Those of ordinary skill in the art will appreciate that in conventional synchronous DRAMs, data presented to the data input/output (DQ) pins are written into a data buffer during either the rising or falling edge of the external clock signal. On the other hand, a recent development in the evolution of synchronous DRAM technology is the so-called “double data rate (DDR) DRAM. In DDR DRAMs, data is written into data buffers on both the rising and falling edges of each clock cycle, thus providing twice as much data as a conventional SDRAM for a given system clock speed. One example of a DDR SDRAM is disclosed in U.S. Pat. No. 6,154,418 to Li, entitled “Write Scheme for a Double Data Rate SDRAM,” which is commonly assigned to the assignee of the present invention and hereby incorporated by reference herein in its entirety.
Due to the high speed data transfers, DDR SDRAMs use a bi-directional data strobe signal (DQS) to register the data being input or output on both edges (rising and falling) of a system clock. According to industry standards, when data is being received by a DDR SDRAM, the DQS has a known latency which can vary between ¾ of a system clock cycle (minimum latency) to 5/4 of the clock cycle (maximum latency). When data is being received by a DDR SDRAM, the system clock cannot be properly synchronized with the DQS because of the latency variation and thus, the system clock cannot be properly synchronized with the input data.
Two parameters of significance to the process of writing data to a DDR DRAM are the setup and hold times specified for the data that is presented to the input buffer. The setup time (DS) is the minimum time in advance of the latching clock (data strobe) edge that valid data must be present at the input buffer's input. The hold time (DH) is the minimum time following the latching clock edge that the data must be present at the input buffer's input. Together, the setup and hold times define a “window” surrounding the data clock edge (rising or falling) during which the data on the data line (DQ) must be valid.
One scheme for clocking data into a DDR DRAM uses a delay element in the write data path to internally delay data relative to the data strobe. By making the delay element variable, the input setup and hold times can be adjusted to ensure that specified setup and hold times are achieved. However, experimental data shows that the setup and hold window can be different for the data clocked in on the rising edge than for the data clocked in on the falling edge. The net effect of this phenomenon is that the total setup and hold window for the input pin is the overlap of the windows for the two clock edges, which can be larger than permissible according to the memory device's specification. Adjustments to the single delay element can help the worst-case setup or hold, but improvement to one (setup or hold) can only be achieved to the detriment of the other.
Thus, it is believed that there remains a need for an improved method and apparatus by which data is clocked in to a DDR DRAM.